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Dual Synchronous Buck Pseudo Fixed Frequency Power Supply Controller
POWER MANAGEMENT Description
The SC1485 is a dual output constant on synchronousbuck PWM controller intended for use in notebook computers and other battery operated portable devices. Features include high efficiency and a fast dynamic response with no minimum on time. The excellent transient response, means that SC1485 based solutions will require less output capacitance than competing fixed frequency converters. The frequency is constant until a step in load or line voltage occurs at which time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. After the transient event, the controller frequency will return to steady state operation. At light loads, Power-Save Mode enables the SC1485 to skip PWM pulses for better efficiency. Each output voltage can be independently adjusted from 0.5V to VCCA. Two frequency setting resistors set the on-time for each buck controller. The frequency can thus be tailored to minimize crosstalk. The integrated gate drivers feature adaptive shoot-through protection and soft switching. Additional features include cycle-by-cycle current limit, digital soft-start, over-voltage and undervoltage protection, and a PGOOD output for each controller.
SC1485
Features
Constant on-time for fast dynamic response Programmable VOUT range = 0.5 - VCCA VIN Range = 1.8V - 25V DC current sense using low-side RDS(ON) sensing or sense resistor Resistor programmable frequency Cycle-by-cycle current limit Digital soft-start Separate PSAVE option for each switcher Over-voltage/Under-voltage fault protection 10uA Typical shutdown current Low quiescent power dissipation Two PGOOD indicators 1% Reference (2% system DC accuracy) Efficiency >90% Integrated gate drivers with soft switching Separate enables 28 Lead TSSOP Industrial temperature range
Applications
Notebook computers CPU I/O supplies Handheld terminals and PDAs LCD monitors Network power supplies
Typical Application Circuit
R1 VBAT R2 9 8 22 TON2 EN/PSV2 EN/PSV1 23 TON1
PGOOD1
27 13
PGOOD1 PGOOD2 VBAT
SC1485
PGOOD2
EN2 EN1
DH2 LX2
20 19 R8 18 16 15 12 26
Q4
L2 VOUT2 Q3 + C8
Q1
6 5 R3 4
DH1 LX1 ILIM1 DL1 PGND1
ILIM2 DL2 PGND2 FBK2 FBK1
VOUT1
L1
R7
R4
+ C7
Q2
2 1
PGND1
R6
R5
PGND1
Revision: October 14, 2004
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SC1485
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter TON1 to AGND1, TON2 to AGND2 DH1,BST1 to AGND1 and DH2,BST2 to AGND2 LX1 to AGND1 and LX2 to AGND2 AGND1 to PGND1, and AGND2 to PGND2 BST1 to LX1 and BST2 to LX2 VCCA1, VDDP1 to AGND1 and VCCA2, VDDP2 to AGND2 FB1, PGOOD1, EN/PSV1, ILIM1, VOUT1, DL1 to PGND1 FB2, PGOOD2, EN/PSV2, ILIM2, VOUT2, DL2 to PGND2 Thermal Resistance Junction to Ambient(5) Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec.
Symbol
Maximum -0.3 to +25.0 -0.3 to +30.0 -2.0 to +25.0 -0.3 to +0.3 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0
Units V V V V V V V V C/W C C C
JA TJ TSTG TLEAD
37 -40 to +125 -65 to +150 300
Electrical Characteristics
Test Conditions: VBAT = 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2=VDDP2=5.0V, VOUT1 = 1.25V, RTON1 = 1M,VOUT2 = 1.25V, RTON2 = 1M
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Input Supplies V C C A 1, V C C A 2 V D D P 1, V D D P 2 VDDP1, VDDP2 Operating Current FB > regulation point, ILOAD = 0A VCCA1, VCCA2 Operating Current FB > regulation point, ILOAD = 0A TON1, TON2 Operating Current Shutdown Current RTON = 1M (300kHz) 5.0 5.0 1 700 15 -5 5 0 -10 10 1 4.5 4.5 5.5 5.5 5 1100 V V A A A A A A
EN/PSV1, EN/PSV2 = 0V V C C A 1, V C C A 2 VDDP1, TON1, VDDP2, TON2
Controller Error Comparator Threshold (FBK1, FBK2 turn-on threshold) Output Voltage Range
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VCCA = 4.5V to 5.5V VBAT = 2V-25V
0.500
0.495 0.5
0.505 VC C A
V V
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SC1485
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2=VDDP2=5.0V, VOUT1 = 1.25V, RTON1 = 1M,VOUT2 = 1.25V, RTON2 = 1M
Parameter
Conditions Min
25C Typ 1660 913 400 Max
-40C to 125C Min 1411 776 Max 1909 1050 550
Units
On-Time, VBAT = 2.5V
RTON = 1M (300kHz) RTON = 500k (600kHz)
ns
Minimum Off Time Line Regulation Error Load Regulation Error VOUT1, VOUT2 Input Resistance FBK1, FBK2 Input Bias Current Over-Current Sensing ILIM Current Current Comparator Offset PSAVE Zero-Crossing Threshold (PGND - LX) Fault Protection Current Limit (Positive) (2) (PGND - LX) RILIM = 5k RILIM = 10k RILIM = 20k Current Limit (Negative) (PGND-LX) Output Under-Voltage Fault Output Over-Voltage Fault Over-Voltage Fault Delay PGOOD Low Output Voltage PGOOD Leakage Current PGOOD UV Threshold With respect to internal reference. With respect to internal reference. FB forced above OV Threshold Sink 1mA FB in regulation, PGOOD = 5V With respect to internal reference. EN/PSV = 5V DL high PGND - ILIM VCCA, VDDP = 4.5V to 5.5V VBAT = 4.5V to 25V ILIM - PGND = 0V to OC Limit EN/PSV = Open
ns %/V % k
0.04 0.3 500 -1.0 +1.0
A
10
9 -10
11 10
A mV
5
mV
50 100 200 -140 -30 +10 2
35 80 170 -200 -40 +8
65 120 230 -100 -25 +12
mV mV mV mV % % s
0.4 1 -10 -12 -8
V A %
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SC1485
POWER MANAGEMENT Electrical Characteristics (Cont.)
Test Conditions: VBAT = 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2=VDDP2=5.0V, VOUT1 = 1.25V, RTON1 = 1M,VOUT2 = 1.25V, RTON2 = 1M
Parameter
Conditions Min
25C Typ 2 4.0 165 Max
-40C to 125C Min Max
Units
PGOOD Fault Delay VCCA Under Voltage Threshold Over Temperature Lockout Inputs/Outputs Logic Input Low Voltage Logic Input High Voltage Logic Input High Voltage EN/PSV1 and EN/PSV2
FB forced outside PGOOD window. Falling (100mV Hysteresis ) 10C Hysteresis
s 3.7 4.3 V C
EN/PSV low EN High, PSV low (Pin Floating) EN/PSV high pullup resistance to VCCA pulldown resistance to AGND 1.5 1.0 2.0 1.2 2.4
1.2 2.4
V V V M
Soft Start Soft-Start Ramp Time Under-Voltage Blank Time Gate Drivers Shoot-Through Delay (4) DL Pull-Down Resistance DL Sink Current DL Pull-Up Resistance DL Source Current DH Pull-Down Resistance DH Pull-Up Resistance DH Sink/Source Current DH or DL rising DL low VDL = 2.5V DL high VDL = 2.5V DH low, BST - LX = 5V DH high, BST - LX = 5V VDH = 2.5V 30 0.8 3.1 2 1.3 2 2 1.3 4 4 4 1.6 ns A A A EN/PSV high to full current limit. SMPS Turn-On 1.6 2 ms ms
Notes: (1) When the inductor is in continuous and discontinuous conduction mode, the output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-side MOSFET. (3) This device is ESD sensitive. Use of standard ESD handling precautions is required. (4) Guaranteed by design. See Shoot-Through Delay Timing Diagram on Page 6. (5) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7.
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SC1485
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Device SC1485ITSTR SC1485ITSTRT(2) Package(1) TSSOP-28 TSSOP-28
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant.
TSSOP-28
Pin Descriptions
Pin # 1 2 3 4 Pin Name PGND1 D L1 VD D P1 ILIM1 Pin Function Power ground. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the gate drivers. Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. See applications section for more information. Switching node inductor connection. Gate drive output for the high side MOSFET switch. Boost capacitor connection for the high side gate drive. Enable/Power Save input pin. Tie to ground to disable SMPS. Tie to +5V to enable SMPS and activate PSAVE mode. Float to Enable SMPS and activate continous conduction mode. Battery input voltage and sets on-time of upper MOSFET by series resistor between input supply and VIN. Output voltage sense input for the SMPS output. Connect to the output of the SMPS. Supply voltage input for the analog supply. Connect through a RC filter. Feedback input for the SMPS. Connect from resistive divider at output to select output voltage from 0.5V to VCCA. Power Good output. Goes high after a fixed clock cycle delay following power up. Analog ground.
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5 6 7 8 9 10 11 12 13 14
LX 1 DH1 BST1 EN/PSV2 TON2 VOUT2 VC C A2 FB K 2 PGOOD2 AGND2
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SC1485
POWER MANAGEMENT Pin Descriptions (Cont.)
15 16 17 18 PGND2 D L2 VD D P2 ILIM2 Power ground. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the gate drivers. Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. See applications section for more information. Switching node inductor connection. Gate drive output for the high side MOSFET switch. Boost capacitor connection for the high side gate drive. Enable/Power Save input pin. Tie to ground to disable SMPS. Tie to +5V to enable SMPS and activate PSAVE mode. Float to Enable SMPS and activate continous conduction mode. Battery input voltage and sets on-time of upper MOSFET by series resistor between input supply and VIN. Output voltage sense input for the SMPS output. Connect to the output of the SMPS. Supply voltage input for the analog supply. Connect through a RC filter. Feedback input for the SMPS. Connect from resistive divider at output to select output voltage from 0.5V to VCCA. Power Good output. Goes high after a fixed clock cycle delay following power up. Analog ground.
19 20 21 22 23 24 25 26 27 28
LX 2 DH2 BST2 EN/PSV1 TON1 VOUT1 VC C A1 FB K 1 PGOOD1 AGND1
Shoot-Through Delay Timing Diagram
LX
DH
DL DL tplhDL tplhDH
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SC1485
POWER MANAGEMENT Block Diagram
PGND1 1 DL1 2 VDDP1 3 LO
REF - 30% REF - 10% REF + 10% UV OV FAULT MONITOR
AGND1 28
PGOOD1
27
+5V
ILIM 1 4 ILIMIT
ZEROI OC
FB1 CONTROL LOGIC PWM OFF ON HI
REF
LX1 5 VOUT1 DH1 6 BST1 7
OT VBAT VDDP VCCA2 VCCA VBAT 8 EN/PSV2 POR/SS OT
9 TON2 +5V VOUT2 10 VOUT2 11 VCCA2
TON
ON OFF PWM
CONTROL LOGIC
TOFF 1.5V
REF OC ISENSE ZEROI 18 ILIM2
FB2
12 FBK2
X3
+ PWM +5V
13 PGOOD2 14 AGND2
FAULT MONITOR
OV UV REF + 10% REF - 10% REF - 30%
FIGURE 1
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+ 1.5V TOFF TON POR/SS VCCA1 HI LO
PWM
X3
26 FBK1
FB1
VCCA1 25 VOUT1 24 TON1 23 VOUT1 +5V
EN/PSV1 22 VBAT VCCA
VDDP
VBAT
21 BST2 20 DH2 19 LX2
VOUT2
FB2
17 VDDP2 16 DL2 15 PGND2
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SC1485
POWER MANAGEMENT Applications Information
+5V Bias Supplies The SC1485 requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator such as the Semtech LP2951A. To minimize channel to channel crosstalk, each controller has 4 supply pins, VDDP, PGND, VCCA and AGND. To avoid ground loops, separate AGND planes are recommended. Each contoller requires its own AGND plane which should be tied by a single trace to the negative terminal of that controller's output capacitor. All external components referenced to AGND in the schematic should then be connected to the appropriate AGND plane. The supply decoupling capacitor for controller 1 should be tied between VCCA1 and AGND1. Likewise, the supply decoupling capacitor for controller 2 should be tied between VCCA2 and AGND2. A single 10 ohm resistor should be used to decouple the VCCA supplies from the main VDDP supplies. PGND can then be a separate plane which is not used for routing traces. All PGND connections are connected directly to this plane with special attention given to avoiding indirect connections which may create ground loops. As mentioned above, the two AGND planes must be connected to the PGND plane at the negative terminal of the respective output capacitors. The VDDP1 and VDDP2 input provides power to the upper and lower gate drivers. A decoupling capacitor for each supply is recommended. No series resistor between VDDP and the 5 volt bias is required. Pseudo-fixed Frequency Constant On-Time PWM Controller The PWM control architecture consists of a constant-ontime, pseudo fixed frequency PWM controller, (Figure 1). The output ripple voltage developed across the output filter capacitor's ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The highside switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time to 400ns typically. On-Time One-Shot (TON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current.
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This input proportional current is used to charge an internal on-time capacitor. The TON time is the time required for the voltage on this capacitor to charge from zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a nearly constant switching frequency without the need of a clock generator.
V TON = 3.3x10 -12 *(RTON + 37x10 3 ) * OUT V IN
+50ns
RTON is a resistor connected from the input supply to the TON pin. The graph on page 16 shows the relationship between RTON and switching frequency. Enable & Psave The SC1485 combines the ENABLE and PSAVE functions into a single pin. When the pin is tied to ground the SMPS is disabled. When it is tied to +5V the SMPS is enabled and PSAVE is active. In order to enter PSAVE, The SC1485 PSAVE comparator will look for 8 consecutive inductor current reversals. When this happens, the controller will switch into PSAVE mode. At the same time, the SC1485 will increase the on-time by 1.5 times its set value. This will increase the ripple current and ripple voltage by 1.5 times their continuous conduction mode (CCM) values. This increase has two benefits. First, the reduction in switching frequency will improve efficiency. Second, hysteresis is added to the PSAVE circuit. This is important because when in PSAVE, the very first time a current reversal does not occur, the SC1485 will exit the PSAVE mode. This allows the device to rapidly respond to transient load conditions, while adding hysteresis to eliminate false PSAVE exits. When the pin is left floating, the pin is internally pulled to 2V, enabling the SMPS in CCM. Output Voltage Selection The output voltage selection is set by the feedback resistors R2 & R3 of Figure 3. The internal reference is 1.5V. The internal feedback pin is multiplied by three to match the 1.5V reference. Therefore the output can be selected to a minimum of 0.5V. The equation for selecting the output voltage based on Figure 3 is:
R2 VOUT = 1 + * 0.5 R3
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SC1485
POWER MANAGEMENT Applications Information (Cont.)
Current Limit Circuit Current limiting of the SC1485 can be accomplished in two ways. First, the device can implement on-state resistance of the low-side MOSFET as the current sensing element (RDSON sensing). Second, the device can accept a resistive element in the low-side source (RSENSE, resistor sensing). The second method offers greater accuracy of the current limit threshold over RDSON sensing, at the added expense of a sense resistor and associated efficiency loss. Whether RDSON sensing or RSENSE resistor sensing is used, a scaling resistor between LX and ILIM is required. This resistor, RILIM, is connected to a 10uA current source within the SC1485 through the ILIM pin. This sets a voltage drop equal to 10uA times RILIM. As the current increases through the lower MOSFET, the phase pin voltage will decrease until the offset voltage caused by RILIM is reached and ILIM < PGND. At this point an over-current trip signal is issued. Current limiting will prevent the firing of a DH on-pulse, thereby reducing the switching frequency. As the frequency decreases, the output voltage will drop until an under-voltage shutdown is reached. The current sensing circuit actually limits the inductor valley current (see Figure 2). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown below:
IL OC (Valley ) = 10 A * RILIM RDS ON
+5V +VIN + +5V +VIN
D1
+
C1
BST DH LX ILIM VDDP DL PGND
7 6 5 4
3
C2
Q1 L1 0.5V - 5.5V
2 1
R1 Q2
SC1485
D2
+
R2 C3 FBK
R3
FIGURE 3
The schematic of RDSON sensing circuit is shown in Figure 3 with RILIM = R1 and RDSON of Q2. Similarly, for resistor sensing, the current through the lower MOSFET and the source sense resistor develops a voltage that opposes the voltage developed across RILIM.When the voltage developed across the RSENSE resistor reaches voltage drop across RILIM, an over-current exists and the high side MOSFET will not be allowed to turn on. The over-current equation when using an external sense resistor is:
IL OC (Valley ) = 10A *
RILIM R SENSE
Schematic of resistor sensing circuit is shown in Figure 4 with RILIM = R1 and RSENSE = R4.
I IL OC (Average) = IL OC (Valley ) + L 2
IPEAK ILOAD ILIMIT
BST DH LX ILIM VDDP DL PGND
D1
C1
INDUCTOR CURRENT
7 6 5 4 3 2 1
C2
Q1 L1 0.5V - 5.5V
Q2 D2 R1
SC1485
+
R2 C3 FBK
R4
R3
TIME Valley Current-Limit Threshold Point
FIGURE 4
FIGURE 2
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SC1485
POWER MANAGEMENT Applications Information
Power Good Output Power good is an open-drain output and requires a pullup resistor. When the output voltage is 10% above or below its set voltage, PGOOD gets pulled low. It is held low until the output voltage returns to within 10% of the output set voltage. PGOOD is also held low during startup and will not be allowed to transition high until the output reaches 90% of its set voltage. There is a slight delay built into the PGOOD circuit to prevent false transitions. Output Overvoltage Protection When the output exceeds 10% of the its set voltage the low-side MOSFET is latched on. It stays latched and the SMPS is off until the enable input or POR is toggled. There is a slight delay built into the OV protection circuit to prevent false transitions. Output Undervoltage Protection When the output is 30% below its set voltage the output is latched in a tristated condition, and the SMPS is off until the enable input or POR is toggled. There is a slight delay built into the UV protection circuit to prevent false transitions. POR, UVLO and Softstart An internal power-on reset (POR) occurs when VCCA exceeds 3V, resetting the fault latch and soft-start counter, and preparing the PWM for switching. VCCA undervoltage lockout (UVLO) circuitry inhibits switching and forces the DL gate driver high until VCCA rises above 4.1V. At this time the circuit will come out of UVLO and begin switching, and the softstart circuit being enabled, will progressively limit the output current over a predetermined time period. The ramp occurs in four steps: 25%, 50%, 75% and 100%, thereby limiting the slew rate of the output voltage. There is 100mV of hysteresis built into the UVLO circuit and when the VCCA falls to 4.0V the output drivers are shutdown and tristated. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on, until DL is fully off, and conversely, monitors the DH output and prevents the low-side MOSFET from turning on until DH is fully off. Be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET.
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The high-side gate driver is equipped with turn-on soft switching to reduce gate drive power dissipation. When a DH turn-on is initiated the pull-up resistance is 10 ohms. This limits the peak high-side gate current before the MOSFET is conducting current. The peak gate current plays a large role in gate driver switching losses. When the high-side MOSFET begins conducting, and LX starts to rise, the pull-up resistance on DH changes to 2 ohms. Design Procedure Prior to any design of a switch mode power supply (SMPS) for notebook computers, determination of input voltage, load current, switching frequency and inductor ripple current must be specified. Input Voltage Range The maximum input voltage (VINMAX) is determined by the highest AC adaptor voltage. The minimum input voltage (VINMIN) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. Maximum Load Current There are two values of load current to consider. Continuous load current and peak load current. Continuous load current has more to do with thermal stresses and therefore drives the selection of input capacitors, MOSFETs and commutation diodes. Whereas, peak load current determines instantaneous component stresses and filtering requirements such as, inductor saturation, output capacitors and design of the current limit circuit. Switching Frequency Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. Inductor Ripple Current Low inductor values create higher ripple current, resulting in smaller size, but are less efficient because of the high AC currents flowing through the inductor. Higher inductor values do reduce the ripple current and are more efficient, but are larger and more costly. The selection of the ripple current is based on the maximum output current and tends to be between 20% to 50% of the maximum load current. Again, cost, size and efficiency all play a part in the selection process.
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SC1485
POWER MANAGEMENT Applications Information (Cont.)
Stability Considerations Unstable operation shows up in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is too low, causing not enough voltage ramp in the output signal. This causes the error amplifier to trigger prematurely after the 400ns minimum off-time has expired. Double-pulsing will result in higher ripple voltage at the output, but in most cases is harmless. However, in some cases double-pulsing can indicate the presence of loop instability, which is caused by insufficient ESR. One simple way to solve this problem is to add some trace resistance in the high current output path. A side effect of doing this is output voltage droop with load. Another way to eliminate doubling-pulsing is to add a 10pF capacitor across the upper feedback resistor divider network. This is shown below in Figure 5, by capacitor C4 in the schematic. This capacitance should be left out until confirmation that double-pulsing exists. Adding this capacitance will add a zero in the transfer function and should eliminate the problem. It is best to leave a spot on the PCB in case it is needed.
+5V +VIN
SC1485 ESR Requirements The constant on-time control used in the SC1485 regulates the ripple voltage at the output capacitor. This signal consists of a term generated by the output ESR of the capacitor and a term based on the increase in voltage across the capacitor due to charging and discharging during the switching cycle. The minimum ESR is set to generate the required ripple voltage for regulation. For most applications the minimum ESR ripple voltage is dominated by PCB layout and the properties of SP or POSCAP type output capacitors. For applications using ceramic output capacitors the absolute minimum ESR must be considered. Existing literature describing the ESR requirements to prevent double pulsing does not accurately predict the performance of constant on-time controllers. A time domain model of the converter was developed to generate equations for the minimum ESR empirically. If the ESR is low enough the ripple voltage is dominated by the charging of the output capacitor. This ripple voltage lags the on-time due to the LC poles and can cause double pulsing if the phase delay exceeds the off-time of the converter. Refering to Figure 5, the equation for the minimum ESR as a function of output capacitance and switching frequency and duty cycle is;
Fs - 200000 1+3 * Fs R2 +R3 * ESR > R3 2* *Cout *Fs *( 1 -D) 2
D1
+
C1
BST DH LX ILIM VDDP DL PGND
7 6 5 4 3 2 1
C2
Q1 L1 0.5V - 5.5V
Where D = Vout/Vin.
R1 Q2
D2
+
R2 C3
C4 10pF
R3 FBK
FIGURE 5
Loop instability can result in oscillations at the output after line or load perturbations that can trip the overvoltage protection latch or cause the output voltage to fall below the tolerance limit. The best way for checking stability is to apply a zero to full load transient and observe the output voltage ripple envelope for overshoot and ringing. Over one cycle of ringing after the initial step is sign that the ESR should be increased.
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SC1485
POWER MANAGEMENT Applications Information (Cont.)
Layout Guidelines - see Application Note AN02-6 1485 System DC Accuracy Three IC parameters affect system DC accuracy, the internal band gap reference, the error comparator offset voltage, and the switching frequency variation with line and load. The internal 1% 1.5V reference contains two error components, a 0.5% DC error and a 0.5% supply and temperature error. The error comparator offset is trimmed so that it trips when the feedback pin is nominally 0.5 volts +/-1% at room temperature. The comparator offset trim compensates for any DC error in the reference. Thus, the percentage error is the sum of the reference variation over supply and temperature and the offset in the error comparator or 1.5%. The on pulse in the SC1485 is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on regulators regulate to the valley of the output ripple, 1/2 of the output ripple appears as a DC regulation error. For example, if the feedback resistors are chosen to divide down the output by a factor of five, the valley of the output ripple will be 2.5V. If the ripple is 50mv with VIN = 6 volts, then the measured DC output will be 2.525 volts. If the ripple increases to 80mv with VIN = 25 volts, then the measured DC output will be 2.540. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation is usually desirable to use passive droop. Take the feedback directly from the output side of the inductor incorporating a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. Board components and layout also influence DC accuracy. The use of 1% feedback resistors contribute 1%. If tighter DC accuracy is required use 0.1% feedback resistors. The output inductor value may change with current. This will change the output ripple and thus the DC output voltage. It will not change the frequency.
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Switching frequency variation with load can be minimized by choosing lower RDSON MOSFETs. High RDSON MOSFETS will cause the switching frequency to increase as the load current increases. This will reduce the ripple and thus the DC output voltage. This inherent droop should be considered when deciding if passive droop is required. If the output ripple some passive droop may be desirable to further reduce the output capacitance. Thermal Considerations The junction temperature of the device may be calculated as follows:
TJ = TA + PD * JA C
Where: TA = ambient temperature (C) PD = power dissipation in (W) JA = thermal impedance junction to ambient from absolute maximum ratings (C/W) The power dissipation may be calculated as follows:
PD = 2 * VCCA * IVCCA + Vg * Q g * f
(
)
W
Where: VCCA = chip supply voltage (V) IVCCA = operating current (A) Vg = gate drive voltage, typically 5V (V) Qg = FET gate charge, from the FET datasheet (C) f = switching frequency (kHz) Inserting the following values as an example: TA = 85C JA = 37C/W VCCA = 5V IVCCA = 1100A (data sheet maximum) Vg = 5V Qg = 60nC f = 300kHz (enter the higher of the two set frequencies here) gives us:
TJ = 85 + 2 * 5 * 1100 * 10 -6 + 5 * 60 * 10-9 * 300 * 103 * 37 = 92 C
(
)
As can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special consideration thermally during layout.
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SC1485
POWER MANAGEMENT Typical Characteristics
SC1485EVB Efficiency at Vout = 1.8V
100 90 Efficiency (%) 80 Efficiency (%) 70 60 50 40 30 20 0.001 0.01 0.1 1 2 3 4 5 6 VIN = 25V VIN=14V VIN=4.5V 90 80 70 60 50 40 0.001 VIN=25V VIN=14V VIN=4.5V 100
SC1485 Efficiency at Vout = 3.3V
0.01
0.1
1
2
3
4
5
6
Output Current (Amps)
Load Current (Amps)
SC1485EVB Load Regulation at Vout = 1.8V
0.3 0.2 Load Regulation (%) Load Regulation (%) 0.1 0 -0.1 0 -0.2 -0.3 -0.4 -0.5 -0.6 Load Current (Amps) 1 2 3 4 5 6 Vin = 25V Vin = 19V Vin = 14V Vin = 10V Vin = 4.5V 0.25 0.2 0.15 0.1 0.05 0 -0.05 -0.1 0
SC1485 Load Regulation at Vout = 3.3V
VIN=25V VIN=19V VIN=14V VIN=10V VIN=4.5V 1 2 3 4 5 6
Load Current (Amps)
SC1485EVB Line Regulation at Vout = 1.8V
2 1.8 Line Regulation (%) Line Regulation (%) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 4.5 10 14 Line Voltage (Volts) 19 25 IL = 0A IL = 1A IL = 2A IL = 3A IL = 4A IL = 5A IL = 6A 1 1.2
SC1485 Line Regulation at Vout = 3.3V
IOUT=0A 0.8 0.6 0.4 0.2 0 4.5 10 14 Input Voltage (Volts) 19 25 IOUT=1A IOUT=3A IOUT=4A IOUT=5A IOUT=6A
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SC1485
POWER MANAGEMENT Typical Characteristics (Cont.)
Load Release 6A - 0A, Forced Continuous Mode L = 2uH, Cout = 600uF, Vout = 1.8V, Vin = 12V, Load Applied 0A - 6A, Forced Continuous Mode L = 2uH, Cout = 600uF, Vout = 1.8V, Vin = 12V,
0A - 6A Transient, Forced Continuous Mode L = 2uH, Cout = 600uF, Vout = 1.8V, Vin = 12V
Forced Continuous Mode to PSAVE Mode
Upper Trace: Inductor Current Lower Trace: Phase Lead
Upper Trace: Inductor Current Lower Trace: Phase Lead
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SC1485
POWER MANAGEMENT Typical Characteristics (Cont.)
Frequency vs Input Voltage (Iout = 1A, Vout = 2.5V, Rton = 1M)
310 Frequency (kHz) Frequency (kHz) 300 290 280 270 260 250 5 10 15 Input Voltage (Volts) 20 25 300 290 280 270 260 250 0 1 2 3 4 5 6 Load Current (Amps)
Frequency vs Load Current (Vin = 15V, Vout = 2.5V, Rton = 1M)
Rton vs Frequency (Vin = 15V, Vout = 2.5V, Iout = 1A)
600 Frequency (kHz) 500 400 300 200 100 0 400 500 600 700 800 900 1000 1500
Rton (kohms)
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SC1485
POWER MANAGEMENT
1.5V @ 3A PGOOD 1
C11 1 C6 2 1 PG 1 ND 2 +
150uF POSCAP
10uF /25V C5 2 1 1 0.1uF /25V Q2 Si4818D Y 20k 10k PG 2 ND 2 L2 R2 2 1 2 5uH R5 470k VD D 1 1M 1 C9 2 0.1uF 1 2 1 R8 6. 19k AG 1 ND PG 2 ND VC CA VD D 0.22uF 1 C10 2 AG 2 14 ND AG 2 ND PG 2 ND 15 R11 VD D 1 2 470k PGOOD 2 1.8V @ 4A VBAT +5V R9 2 1 R10 2
8
3
2
1 5 6
7
D2 1 2
28
27
26
25
VC CA
MBR0530
F BK1
24
VO UT1
23
22
21
20
19
18
17
4
PGOOD 1
VO UT1
BST2
EN /PSV1
AG 1 ND
VC CA1
TON1
ILIM2
F BK1
LX2
VD DP2
1 C1 2 CA 2 VC 0.22uF
ILIM1
BST1
TON2
1
10
VC CA 11
12
F BK2
DH 1
LX1
DL1
10
VC CA 8
VD D
D1 1 2 2 VD D R3 8. 45k 2 1 C8 1
MBR0530 C4 2 C3 2 1 1
2
R7 1.5M VBAT1
0.22uF 0.1uF
10uF /25V 2 C2 D1 2 1 8 0.1uF /25V 7 4
1G
6 S1 1 5
D1
1G
D1
D1
S1
3
Q1A F DS6982S 1
Q1B D3 F DS6982S 2 L1 1
MBR0530
VOUT1 2
3.3uH C7 1 2 +
VO UT1
F 150uF POSCAP BK1 R4 1 R6 1 2 AG 1 ND F BK1
2
20k
7. 68k
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PG 1 ND
13
1
2
3
4
5
6
7
9
PGOOD 2
EN /PSV2
R1 PG 1 ND VD DP1
SC1485
DH 2
VO UT2
VC CA2
DL2
16
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SC1485
POWER MANAGEMENT Outline Drawing - TSSOP-28
A e N 2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123 E D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.047 .002 .006 .031 .042 .007 .012 .003 .007 .378 .382 .386 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 28 0 8 .004 .004 .008 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 9.60 9.70 9.80 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 28 0 8 0.10 0.10 0.20
e/2 B D A2 A
aaa C SEATING PLANE
C
bxN bbb
A1 C A-B D GAGE PLANE 0.25
H c
L (L1) DETAIL
01
SIDE VIEW
SEE DETAIL
A
A
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AE.
Land Pattern - TSSOP-28
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2004 Semtech Corp. 17 www.semtech.com

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